https://github.com/kunmok/digital_backend_for_128GSPS_ADC

This repository contains a collection of SystemVerilog RTL files for the digital backend implementation of the 128 GS/s ADC-based SerDes receiver.

This work is a collaboration between Sunjin and me — we jointly developed the digital backend and DSP architecture, while Sunjin carried out the full RTL implementation and place-and-route (P&R).

Unfortunately, we had to remove certain SDC constraint files and Hammer setup scripts because they contained sensitive PDK information. As a result, the version available in this repository is not the complete version used for tapeout. Nevertheless, it still provides sufficient detail to understand the overall architecture, retiming strategy, memory implementation, and the nonlinear feed-forward equalizer we developed.

We are also preparing a separate paper that discusses the detailed theory and operation of the nonlinear equalizer — referred to as the pattern-detection MLSE — which will be submitted to an IEEE journal in the near future. Stay tuned !!!