A 128 GS/s 16x-Interleaved 6-Bit ADC Design for Wireline Communication
Coming Soon …
Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers
In this paper, we propose a feed-forward nonlinear equalizer capable of canceling both pre-cursor and post-cursor ISI in an ADC-based wireline receiver system.
Accurate Statistical BER Analysis of DFE Error Propagation in the Presence of Residual ISI
We investigate an accurate statistical modeling and analysis methodology for DFE error propagation in the presence of residual ISI.