A 128 GS/s 16x-Interleaved 6-Bit ADC Design for Wireline Communication
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Wireline
Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers
In this paper, we propose a feed-forward nonlinear equalizer capable of canceling both pre-cursor and post-cursor ISI in an ADC-based wireline receiver system.